1. Field of the Invention
This invention relates to surface mount technology using leadless integrated electronic circuit components and in particular to systems and methods for minimizing stress between the leadless component and the printed circuit (PC) board.
2. Description of Background Art
Surface mount technology offers several advantages for electronic equipment manufacturers including the critical advantage of increased component packing density. One of the biggest demands for surface mount technology in the surface acoustic wave (SAW) device industry comes from the cellular and cordless telephone market. The "cigarette pack" is being replaced by the "telephone pack". For the electronic equipment manufacturer, surface mount technology carries with it a difficult solder joint thermal mismatch problem between the component or surface mount package and the PC board. The thermal mismatch problems are especially acute for low frequency and narrow bandwidth SAW devices where the package size can be relatively large. These problems often rule out off-the-shelf options and therefore confront the SAW manufacturer with high package tooling costs.
The coefficient of thermal expansion (CTE) is a number that represents the dimensional change of a material over a specific temperature range. By way of example, a well accepted mounting arrangement for mounting a surface mount package (SMP) which is carrying a SAW device is to solder the ceramic bases onto a copper clad PC board material using a lead and tin alloy solder paste. The thermal profile during solder paste reflow typically exceeds 200.degree. C. for short periods of time. The CTE of the epoxy and glass PC board material is approximately three times greater than the ceramic material used in the package and occasionally less than half the CTE of the solder alloy that joins the two. Effects of the thermal mismatch are first encountered during the cool down period after the solder is reflowed during initial attachment. The molten solder will solidify just below 200.degree. C. and at that time the assembly is mechanically fixed and as near stress free as possible. As the temperature continues to decrease, the differing expansion rates begin to become a factor. The PC board material decreases in size at a ratio of about three to one with respect to the SMP ceramic substrate. The solder alloy decreases by as much as two to one relative to the PC board and six to one relative to the ceramic. As the relative locational association of the solder pads on the ceramic and PC board begins to change, mechanical stress increases in all three components (the ceramic, the PC board, and the solder joint). The solder joint is usually the weakest of the three and as a result breakage occurs in the joints at various stress points depending on the specific alloy being used.
One factor that complicates the identification of over stressed joints is that the joints are most likely to degrade but not completely fail. In other words, they may remain electrically active for some period of time and then experience failure. While the first cool down period after reflow begins the process of mechanically degrading the solder joint, the joints are most likely to fail after some number of thermal cycles during the normal life environment. Another situation includes the intermittent electrical failure of the solder joint. The indication is that a particular joint functions normally and displays no problems except for this intermittent open indication that may exist for very short periods during some portion of the thermal cycle. The relative movement created by the CTE mismatch is sufficient to move a break in the solder joint into and out of electrical contact. Such failures are difficult to detect and require more extensive testing including greater attention to the temperature cycles used and continuous monitoring during the cycles.
As discussed, more and more demands are being made for providing compact instruments such as the cellular telephone that fits in the breast pocket. Leadless packages are therefore very desirable for meeting the size efficiency demands. Leaded components (as in electrical lead) relieve the stress problems but take up valuable "real estate" in doing so. Leadless chip carriers offer attractive size efficiency but suffer thermal mismatch and crosstalk problems. Several options are available to the industry that meet many of the requirements. Packages are supplied with either flat leads or simple terminations. Leads may exit from the sides of the package and transition to the board level as in "gull-winged" and "J-lead" designs. Alternatively, the may exit from the bottom and either be flat or tuck underneath the package as in the "C-lead" configuration. The gull-wing or flat approaches are simple but waste precious PC board area. The J-lead and C-lead raise the base further off the PC board than alternative techniques, resulting in not only increased volume requirements for a device but higher crosstalk and lead inductance.
It is also well known in the art to increase the height of the solder column between the package terminal pad and PC board terminal pad. Increasing the height of a column with a fixed SMP footprint spreads the total stress over a greater mass and ultimately decreases the stress per unit mass. The column deals with the relative pad movement by bending as opposed to shearing. Since the stress levels per unit mass can be maintained at a level that does not cause creep to occur, the joint will survive thermal cycles. Although this approach is simple in concept, there are problems in the implementation of such a mounting scheme. Foremost is the difficulty in increasing solder column height for a given footprint using standard production assembly techniques. By way of example, many factors must be considered including the solder alloy used, special tooling and fixturing to elevate the SMP during reflow, and cleaning and inspection problems that result from the use of non-removable spacers between the part and the PC board.
U.S. Pat. No. 4,847,136 issued to Ching-Ping Lo on Jul. 11, 1993 discloses a thermal expansion mismatch forgivable printed wiring board for a ceramic leadless chip carrier. A PC board is fabricated wherein a thin expansion layer is provided on top of what would be considered a conventional PC board. This expansion layer is bonded to the PC board except at locations underneath the footprint of the chip carrier and solder joints. This expansion layer reduces the stress of the solder joints between the ceramic leadless chip carrier and the PC board due to thermal expansion mismatch, thus reducing the cracking of the solder joint. As is well known in the art, metal plates are added as part of the PC board where it is desirable to thermally conduct heat away from the PC board and where added strength is required. U.S. Pat. No. 4,658,332 issued to Thomas E. Baker et al. on Apr. 14, 1987 teaches a compliant layer PC board.
U.S. Pat. No. 4,641,222 issued to Dennis J. Derfiny et al. on Feb. 3, 1987 discloses a mounting system for stress relief in surface mounted components. The PC board is conditioned by removing selected areas of media surrounding the points of attachment between the surface mounted component and the PC media. In addition, a spacing element is disposed between the surface mounted component and the PC board to promote the formation of a virtual lead during assembly. U.S. Pat. No. 4,654,248 issued to Juzer Mohammed on Mar. 31, 1987 teaches a PC board with zones of controlled thermal coefficient of expansion.
U.S. Pat. No. 4,554,575 issued to Michael R. Lucas on Nov. 19, 1985 teaches a low stress leadless chip carrier and method for assembly to a PC board. A plurality of castellations are provided in the perimeter walls of the carrier member and solder preforms are deformably fitted in the castellations for reflow vapor phase soldering to a PC board. A spacer member is disposed between the carrier member and the printed circuit board and has a CTE matched to that of the solder. The spacer includes a high thermal conductivity planar metal portion sandwiched between an adhesive epoxy layer which facilitates assembly of the carrier to the PC board.
While there has been an effort to solve solder joint stress failures caused by thermal mismatch, the need to provide an effective packaging method that meets the needs for simple fabrication having reduced joint failure due to thermal stress problems and reduced crosstalk has not been provided.